Method for operating an error protected multiprocessor central control unit in a switching system

US4914572A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Rudolf Bitzinger · Munich, DE
• Walter Engl · Feldkirchen-Westerham, DE
• Siegfried Humml · Penzberg, DE
• Klaus Schreier · Penzberg, DE

Key dates

• Filing date: Mar 11, 1987
• Grant date: Apr 3, 1990
• Expiry date: Mar 11, 2007

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04Q3/54591
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method provides error protection in a multiprocessor central control unit of a switching system wherein a number of central processors (CP, IOC) as well as a central memory (CMY) are connected in parallel to a central bus system (B:CMY0/B:CMY1). The processors include dual highly-synchronous parallel driven processor units (PU) --apart from a possible tolerable positive timing slip--and integral error detection circuits (V), as well as an integral local memory (LMY), in the ROM-area of which test program sections are stored for testing the respective processors (CP, IOC). Upon the detection of an error by at least one of the error detection circuits (V) of a processor (for example CPx), in the respective processor (CPx), at least if the error is not immediately correctable, the error detection circuit (V in CPx) starts isolating the respective processor (CPx) from the bus system (B:CMY). The respective processor (CPx) starts the read-out of the test program sections, stored in its own local memory (LMY), for localizing and identifying the error source and/or the defect causing such errors.