Communication system having interrupts with dynamically adjusted priority levels
US4914580A · kind A · utility
30Cited by
14References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1987 |
| Grant date | Apr 3, 1990 |
| Priority date | — |
| Expiry date | Oct 26, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A communication system includes a processor, memory circuits and a plurality of interfaces for interfacing to data devices. The processor services the interfaces using an interrupt bus including unidirectional inbound and outbound buses. The inbound bus includes one lead for each interface, with each lead having a fixed priority level assigned by the processor. Each interface has access to all leads of the inbound bus. The processor sends commands over the outbound bus to dynamically control the connection of an interface to a lead of the inbound bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.