Inter-processor communication protocol
US4914653A · kind A · utility
105Cited by
9References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1986 |
| Grant date | Apr 3, 1990 |
| Priority date | — |
| Expiry date | Dec 22, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Processors (101) of a multiprocessor system (FIG. 1) communicate across bus (150) via a low-latency packet protocol featuring per-logical channel input queues (143) and output queues (144), different per-processor priorities for sending data packets (FIG. 10) and data packet-acknowledging "quick" messages (FIG. 11), and separate buffers (923; 918) for receiving data packets and "quick" messages, respectively. Transmitted data packets afflicted by error, receive buffer overflow, and input queue-full conditions are discarded by the receiving processor and are retransmitted by the sending processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.