Charge amplifying trench memory cell
US4914740A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 7, 1988 |
| Grant date | Apr 3, 1990 |
| Priority date | — |
| Expiry date | Mar 7, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A charge amplifying memory cell and its memory of making based on trench technology. A trench is formed which reaches through an n-type well region to a p.sup.+ -type substrate. A triple layer is formed on two sidewalls of the trench consisting of two capacitive insulating layers and a intermediate p.sup.+ polysilicon layer. The trench is then at least partially filled with a conductor, such as polysilicon, facing the triple layer. Thereby, the intermediate polysilicon layer acts as a charge storage node with capacitance to both the substrate and the polysilicon filling the trench. The insulating layer facing the well is opened with a contact hole near its top so that a p.sup.+ transistor drain is formed in the adjacent well by diffusion from the polysilicon through the contact hole. A p.sup.+ transistor source is doped into the well with a gate region between it and the drain to provide a write transistor. A p+ region is also formed adjacent a sidewall of the trench other than the one containing the contact hole so that a read transistor is vertically formed in the n-type well between it and the substrate. The intermediate p.sup.+ polysilicon layer acts as the electrode of this re…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.