High performance sidewall emitter transistor
US4916083A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1989 |
| Grant date | Apr 10, 1990 |
| Priority date | — |
| Expiry date | Mar 6, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/281
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A novel vertical bipolar device endowed with a lithography-independent tightly controlled submicron-wide emitter. In one embodiment, the emitter is contacted by a self-aligned conductive sidewall linked up to a horizontal conductive link. The extrinsic base, embedded within the collector, is recessed below and laterally spaced from the emitter by an insulator layer formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In a third embodiment, the emitter is ring shaped. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area. A novel process of forming vertical (e.g. NPN) bipolar device in which starting with a substrate having an N type epitaxial collector region, a horizontal layer composed of oxide-polysilicon dual layer with a substantially vertical surface is formed. P typ…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.