Pipelined parallel data processing apparatus for directly transferring operand data between preceding and succeeding instructions
US4916606A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1987 |
| Grant date | Apr 10, 1990 |
| Priority date | — |
| Expiry date | Jul 20, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus of processing first instruction of a type in which the result of operation of the first instruction is stored in at least one storage location designated by operands of the first instruction and second instruction of a type which succeeds to the first instruction and makes use of the result of operation of the first instruction as operand data. The apparatus comprises an OSC control circuit for detecting whether at least a part of the result of operation of the first instruction is to be used or not as the operand data for the second instruction, and an arithmetic unit for allowing the result of operation of the first instruction to be directly used as the operand data for the second instruction when the OSC control circuit detects the given condition is fulfilled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.