Floating point processor architecture
US4916651A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1988 |
| Grant date | Apr 10, 1990 |
| Priority date | — |
| Expiry date | Jan 29, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating point processor (10) is provided having a multiplier (48) and an ALU (54) for performing arithmetic calculations simultaneously. The output of the multiplier (48) and ALU (54) are stored in a product register (64) and a sum register (66), respectively. Multiplexers (40,42,44,46) are provided at the inputs to the multiplier (48) and the ALU (54). The multiplexers choose between data in input registers (32,34), product and sum registers (64,66), and an output register (76). Since the multiplier (48) and ALU (54) operate simultaneously, and since the outputs of the multiplier (48) and ALU (54) are available to the multiplexers (40-46), product of sums calculations and sum of products calculations may be performed rapidly. An input stage (12) uses a temporary register (18) to store data from a data bus on the first clock edge, and configuration logic (28) for directing data from the data bus and the temporary register (18) to the input registers (32,34) on a second clock edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.