Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures
US4916652A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1987 |
| Grant date | Apr 10, 1990 |
| Priority date | — |
| Expiry date | Sep 30, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3889
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic multiple instruction stream, multiple data, multiple pipeline (MIMD) apparatus simultaneously executes more than one instruction associated with a multiple number of instruction streams utilizing multiple data associated with the multiple number of instruction streams in a multiple number of pipeline processors. Since instructions associated with a multiple number of instruction streams are being executed simultaneously by a multiple number of pipeline processors, a tracking mechanism is needed for keeping track of the pipe in which each instruction is executing. As a result, a dynamic history table maintains a record of the pipeline processor number in which each incoming instruction is executing, and other characteristics of the instruction. When a particular instruction is received, it is decoded and its type is determined. Each pipeline processor handles a certain category of instructions; the particular instruction is transmitted to the pipeline processor having its corresponding category. However, before transmission, the pipeline processor is checked for completion of its oldest instruction by consulting the dynamic history table. If the table indicates that the ol…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.