Elongated burst trapping
US4916702A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 1988 |
| Grant date | Apr 10, 1990 |
| Priority date | — |
| Expiry date | Jun 17, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/27
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an error trapping decoder in which a received codeword is shifted through a re-encoder shift register to produce a set of r syndrome characters and in which the encoder shift register is then isolated and its contents shifted until a number of consecutive zero virtual check characters is produced therein, the capacity to trap long error bursts is enhanced by increasing the size of the code and by demanding that the minimum number of consecutive zero virtual check characters be only sufficient to ensure an acceptably low probability that one or more of the zero-value virtual check characters is a false indication. Such a decoder may be used to determine the location of an error burst in a received block of interleaved codewords as long as at least one of the codewords in the block produces the minimum number of consecutive zero-value virtual check characters after a requisite number of shifts of the encoder. Upon this occurrence, the codeword locations of the non-zero-value virtual check characters are designated as erasure locations for the rest of the codewords in the block, thus enabling all of them to be decoded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.