Drain-biassed transresistance device for continuous time filters
US4918338A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 4, 1988 |
| Grant date | Apr 17, 1990 |
| Priority date | — |
| Expiry date | Oct 4, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A tunable drain-biased transresistance (DBT) device for generating accurate linearly variable RC values employs first and second matched MOS transistors connected in first and second series circuits with third and fourth matched MOS transistors, respectively, across the terminals of a source of supply voltage. A differential amplifier has first and second input terminals connected to respective drain electrodes of the first and second MOS transistors and an output coupled via a feedback circuit to at least one of its input terminals. A pair of signal input terminals are connected to the gate electrodes of the first and second transistors so that said input terminals operate into a high impedance. A source of adjustable bias voltage (V.sub.B) is connected in common to the gate electrodes of the third and fourth transistors thereby to supply adjustable bias currents (I.sub.B) to the drain electrodes of the first and second transistors so as to bias these transistors into their triode regions. The tunable DBT device thereby exhibits a wide dynamic linear input range. The resistance of the device is adjustable in a linear manner by controlling the drain voltage of the first and second …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.