Extended memory device with instruction read from first control store containing information for accessing second control store
US4918586A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1986 |
| Grant date | Apr 17, 1990 |
| Priority date | — |
| Expiry date | Jul 30, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0638
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device provided on a one-chip microcomputer includes a high-speed ROM and a low-speed ROM which are arranged in the same address space and thus can be addressed by the same address pointer, wherein information requiring a high-speed operation and/or having a high access frequency is stored in the high-speed ROM and information requiring no high-speed operation and/or low access frequency is stored in the low-speed ROM. Another memory includes a pair of first and second memories, wherein the first memory includes an extended instruction for accessing the second memory, which thus serves as a virtual memory. The second memory is accessed only when reference is made to an address of an operand of an instruction which immediately follows the extended instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.