Adder cell having a sum part and a carry part

US4918640A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Wolfgang Heimsch · Munich, DE
• Ernst Muellner · Munich, DE

Key dates

• Filing date: Jan 12, 1989
• Grant date: Apr 17, 1990
• Expiry date: Jan 12, 2009

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2207/4806
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

An adder cell having a sum part and a carry part, whereby the sum part and the carry part each contain differential amplifiers having exclusively bipolar or ECL technology as well as differential amplifiers having mixed bipolar MOS transistors. The processing speed can be considerably increased with such an arrangement in comparison to exclusive CMOS adder cells. Additionally, the adder cell carries out a level conversion of CMOS input levels to ECL output levels, so that CMOS levels between 0 and 5 volts can be received at the first four inputs (E1, E2, E3, E4) and ECL boosts in the millivolt range can be taken at the sum outputs (S, S) or, at the carry outputs (CO, CO).