Method and circuitry for compensating for negative internal ground voltage glitches
US4920286A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1986 |
| Grant date | Apr 24, 1990 |
| Priority date | — |
| Expiry date | Jul 2, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00353
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The specification discloses circuitry for compensating integrated circuits for negative internal ground voltage glitches. An output transistor (30) receives input signals at its base and has an emitter connected through a Schottky diode (32) to internal circuit ground. The compensation circuit includes a transistor (42) coupled to the base of transistor (30) and having an emitter also coupled to internal circuit ground. A capacitor (44) is connected between the base of transistor (42) and a source of bias voltage. Transistor (42) is rendered conductive by the occurrence of negative voltage glitches on the circuit ground, thus reducing voltage on the base of transistor (30) to prevent premature conduction by transistor (30).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.