Output buffer having reduced electric field degradation
US4920287A · kind A · utility
11Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1988 |
| Grant date | Apr 24, 1990 |
| Priority date | — |
| Expiry date | Nov 1, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital circuit with a 5 V power supply voltage in which NMOS transistors constructed in sub-micron technology are protected against excessive field strengths by means of additional transistors in order to prevent so-called "hot carrier stress" for this purpose the additional transistors have a greater channel length and/or a higher threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.