Wafer scale package system and header and method of manufacture thereof
US4920454A · kind A · utility
23Cited by
17References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1988 |
| Grant date | Apr 24, 1990 |
| Priority date | — |
| Expiry date | Jul 1, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a wafer scale device 10, 201 on which is formed a layer of thin film as an interconnection system 203 with contact sites 202, 207 between the interconnection system 203 and die bonding sites 202 of the wafer 10, 201 to form a monolithic wafer. The interconnection system 203 has bonding sites on the surface of the wafer 10, 201 to which chips 11 are bonded to form a hybrid monolithic wafer system. The wafer 10 is packaged within a wafer package, FIG. 4, and the packaging system utilizes a header 20 which is a flexible circuit connector between the wafer package and first level circuit board 30.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.