Demultiplexer system
US4920535A · kind A · utility
54Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1988 |
| Grant date | Apr 24, 1990 |
| Priority date | — |
| Expiry date | Dec 14, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/047
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A demultiplexing circuit includes a frame synchronization circuit which simultaneously detects the occurrence of a predetermined frame synchronization pattern and the occurrence of a predetermined identification byte within the frame synchronization pattern. Since the pattern and identification bit are detected simultaneously and from the same data, the circuit is simplified and the demultiplexing is performed more quickly and efficiently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.