Error recovery scheme for destaging cache data in a multi-memory system
US4920536A · kind A · utility
10Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1988 |
| Grant date | Apr 24, 1990 |
| Priority date | — |
| Expiry date | Oct 14, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system in which a processor has a cache receiving data staged from at least two main memories. Performance is enhanced by providing an indicator identifying the main memory from which data is staged. When data in the cache is destaged, the indicator is used to direct the destaged data to the proper main memory. If an error occur in the indicator, the data will be destaged to each main memory where a check is made on the address of the data to determine whether the main memory is the source of the destaged data. The data is stored in a main memory only if the memory is the source thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.