Memory error correction system
US4920539A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 20, 1988 |
| Grant date | Apr 24, 1990 |
| Priority date | — |
| Expiry date | Jun 20, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for correcting soft memory failures such as alpha particle failures in a dynamic random access memory and in a computer system wherein writeback caches are employed in a system bus environment. The address field and source identification code associated with a detected data error are stored. A generic bus request signal is generated and upon a bus grant a read message is issued on the system bus having an address field and destination address code corresponding to the stored address field and source identification code. In response to the read message, the device indicated by the identification code writes back to memory the correct data corresponding to the address field.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.