Frame synchronizing apparatus
US4920546A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1988 |
| Grant date | Apr 24, 1990 |
| Priority date | — |
| Expiry date | Mar 31, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0605
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Disclosed is a frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication. The digital signals consists serial signals at a rate of f.sub.0 (bps). The serial signals include a frame synchronizing signal consituting n bits or a part of the frame synchronizing signal, collectively arranged in one frame. To attain a high-speed operation and a shorter synchronization establishing time, the apparatus comprises a latching circuit for converting the serial signals into parallel signals and for latching the parallel signals, and a circuit for detecting a plural number of times of synchronization during the n bit interval in one frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.