Circuit for the detection of address transitions
US4922122A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 1988 |
| Grant date | May 1, 1990 |
| Priority date | — |
| Expiry date | Aug 23, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for the detection of address transistions in an integrated circuit comprises a logic signal input terminal, a D flip-flop for memorizing the state of the input signal, and a comparator having a first input terminal connected to the logic signal input terminal and a second input terminal connected to the output terminal of the memorizing means. The comparator gives a first logic level when its input terminals receive a same logic signal level and a second logic signal level when its input terminals receive different logic signal levels. This circuit enables the generation of an output pulse as soon as there is an input address transition, in such a way that the time delay of the output with respect to the address transition is kept to a minimum and the duration of the pulse is suitable for use in the integrated circuit which is sought to be activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.