CMOS/NMOS integrated circuit with supply voltage delay variation compensation
US4922140A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1989 |
| Grant date | May 1, 1990 |
| Priority date | — |
| Expiry date | Mar 17, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS/NMOS integrated circuit realizes individual logic circuits with a combination of CMOS and enhancement-mode NMOS devices. The parameters of the CMOS and NMOS devices are selected such that the supply voltage dependency of the CMOS devices is offset by the supply voltage dependency of the NMOS devices. Thus, the propagation delays in the CMOS and NMOS devices, individually a function of supply voltage, remain constant for variations in the supply voltage. The logic circuits include analog-to-digital converters, adders, multipliers, flip flops and ring oscillators. The ring oscillator includes two blocks of inverters. The first block comprises CMOS inverters connected in series; the second block comprises enhancement-mode NMOS inverters connected in series. The output of the first block is connected to the input of the second block, and the output of the second block is connected to the input of the first block, thus forming a "ring" of inverters. Because the supply voltage dependency of the CMOS inverters is offset by the supply voltage dependency of the NMOS inverters, the oscillation frequency of the ring oscillator is independent of the supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.