Phase-locked loop delay line
US4922141A · kind A · utility
198Cited by
11References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1988 |
| Grant date | May 1, 1990 |
| Priority date | — |
| Expiry date | Jun 3, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for providing precise delays includes a phase-locked loop driven by a reference frequency source such as a crystal oscillator and including a variable delay circuit. The output of the oscillator is applied to the delay circuit and the non-delayed and delayed signals are compared in a phase comparator. An error signal representative of phase error is developed and applied to vary the amount of delay until the phase error is eliminated. A precise delay referenced to the oscillator frequency is therefore achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.