Folded extended window field effect transistor
US4922311A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1989 |
| Grant date | May 1, 1990 |
| Priority date | — |
| Expiry date | Apr 11, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/915
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate electrode having an insulating top layer as well as insulating sidewall spacers permits the source and drain regions to be electrically contacted through windows directly above the source and drain regions formed in a window pad layer. There is a conducting layer, termed a window pad layer, over portions of these regions. Because of the insulating top layer and sidewall spacers on the gate, the window may be misaligned with respect to the source and drain regions, and maybe even closer to the gate than are these regions, but electrical contacts to these regions are still obtained. The window pad layer may also be used as sublevel interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.