Gate array device having a memory cell/interconnection region
US4922441A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1988 |
| Grant date | May 1, 1990 |
| Priority date | — |
| Expiry date | Jan 14, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/90
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A gate array device includes a plurality of basic cell regions spaced apart from one another to thereby define a plurality of intermediate regions therebetween. Each intermediate region may serve either as a memory or function cell region or as an interconnection region at least partly. The memory cell region may be selectively defined as a ROM or a RAM by metallization. A test mode or a normal operating mode may be set selectively in accordance with a control signal. When the normal operating mode is set, an input terminal is operatively connected to a memory circuit through a logic circuit; whereas, when the test mode is set, the input terminal is directly connected to the memory circuit while bypassing the logic circuit. Also provided is a memory cell structure which can be defined as a RAM memory cell or as a ROM memory cell storing a selected binary data by metallization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.