Memory re-mapping in a microcomputer system
US4922451A · kind A · utility
77Cited by
23References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1989 |
| Grant date | May 1, 1990 |
| Priority date | — |
| Expiry date | Aug 7, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microcomputer system has a first, low order address, memory soldered to the planar printed circuit board and can accept further memory pluggable into a socket on the board. At power on self test, the memories are tested, and, if an error is detected in the first memory, this memory is disabled by directing the lowest order memory addresses to the second memory and reducing the highest order addresses by the number of locations in the first memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.