Method of reducing wearout in a non-volatile memory with double buffer
US4922456A · kind A · utility
33Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1988 |
| Grant date | May 1, 1990 |
| Priority date | — |
| Expiry date | Apr 29, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3495
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of preventing a power failure from corrupting data being written to a non-volatile memory. Before a write operation is performed, information is written to a double buffer to reconstruct the steps that will be performed during the write operation. A flag is set indicating that the information in the double buffer is accurate. The write operation is then performed and the flag is cleared. The double buffer is dynamically moved throughout the non-volatile memory to distribute the wearout of the non-volatile memory as evenly as possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.