Error detection and correction circuit
US4922493A · kind A · utility
8Cited by
8References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 15, 1988 |
| Grant date | May 1, 1990 |
| Priority date | — |
| Expiry date | Aug 15, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An overload circuit detects input signals that are too high or too low in amplitude and generates a holding signal of a predetermined duration. The holding signal is applied to a data selector which normally passes the input signal to a shift register/majority gate but switches to supply the output of the majority gate to the shift register when a holding signal is present. Thus, the output is maintained constant during the predetermined durations when a holding singnal is present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.