Input protecting circuit in use with a MOS semiconductor device
US4924339A · kind A · utility
14Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1988 |
| Grant date | May 8, 1990 |
| Priority date | — |
| Expiry date | Dec 28, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
Abstract
A bipolar transistor for clamping an excess input potential is provided near an input pad. A signal from the input pad is supplied through a wire to the gate of a MOS transistor in the input stage. A diode is provided near the gate of the MOS transistor. The diode absorbs a potential oscillation generated in the wire near the gate of the transistor, which is due to action of an inductance involved in the wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.