Bifurcated register priority system
US4926313A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1988 |
| Grant date | May 15, 1990 |
| Priority date | — |
| Expiry date | Sep 19, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual priority hold register enables the transfer of data to memory ports having serial priority in accordance with two stages of priority. First, all latches of a high priority sector of the register are cleared. Then, the highest priority latch of the low priority sector of the register is cleared, while the latches of the higher priority register are loaded with further data. Following clearance of the low priority latch, all latches of the higher priority register are cleared once again, followed by clearance of the next highest priority latch of the lower priority register sector while the higher priority register is loaded once again. The sequence is repeated until both the higher and lower priority sectors of the register are clear.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.