Static ram with write recovery in selected portion of memory array
US4926384A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 27, 1988 |
| Grant date | May 15, 1990 |
| Priority date | — |
| Expiry date | Jul 27, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory has a multiplicity of separate memory blocks, only one of which is activated during each memory access cycle. Each memory block has its own separate bit line equalization circuity which equalizes the voltages of each complementary bit line pair in the memory block. A write equalization decoder automatically, at the end of each write cycle, generates a decoded write recovery equalization pulse, which activates the bit line equalization circuitry only in the memory block to which data has been written. As a result, the process of equalizing the bit lines is removed from the critical timing path for accessing the memory after a write cycle, eliminating one of the primary problems associated with the use of address transition detection in static memory devices. In addition, the write recovery equalization pulse can be generated at high speed because the decoded write recovery equalization pulse drives only one of the multiplicity of separate memory blocks. In another aspect of the invention, the memory has a plurality of pairs of common data out lines. A plurality of bit lime pairs are coupled to each pair of common data out lines. Common data out line equ…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.