Method and facilities for hybrid packet switching
US4926416A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 1988 |
| Grant date | May 15, 1990 |
| Priority date | — |
| Expiry date | Dec 16, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5649
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In fast packet-switching networks, packets of particular connections (CS1, CS2) (e.g., voice, moving-image) are to be treated with priority over packets of other connections (PS1, PS2, PS3) (e.g., data) (without delay jitter and loss of information). Prior art arrangements are divided into a circuit-switching portion (for CS1, CS2) and a packet-switching portion (for PS1, PS2, PS3). The circuit-switching portion operates on a time-division multiplex basis. On each incoming line, 70 packets each containing 40 octets, for example, are combined into a frame. If no special steps were taken, delays on the order of 40.times.70.times.8 bits=22,400 bits would result in each switching stage; for each input of a switching stage, 22,400 bits of storage would be necessary. According to the invention, all packets are divided within the exchange, into subpackets of equal length and distributed to subframes. Switching takes place on the basis of subframes. Delays and memory location requirements are reduced in the ratio of frames:subframes. Preferably, the connections (CS1, CS2) to be treated with priority are assigned fixed positions in each frame and each subframe throughout the call. Subpacket…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.