System for testing digital circuits

US4926425A · kind A · utility

Assignee

• Robert Bosch GmbH · DE

Inventors

• Rolf Hedtke · Darmstadt, DE
• Rolf Loos · Eppertshausen, DE
• Roland Mester · Darmstadt, DE
• Jurgen Hansel · Darmstadt, DE

Key dates

• Filing date: Jun 9, 1988
• Grant date: May 15, 1990
• Expiry date: Jun 9, 2008

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/221
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Test node equipment is provided between successive component groups operating in cascade and each test node is connected to a data bus system through which test patterns can be provided by a test pattern generator and from which signals can be evaluated by a test pattern analyzer, the test pattern generator and the test pattern analyzer being under control of a test computer. Each test node has a state in which the output of the preceding component group passes through it to the next component group with only a possibility of monitoring possible deficiencies by the test computer and other states in which the cascade operation of component groups can be interrupted at a test node for inserting a test pattern to a following component group or receiving a processed test pattern from a preceding component group. A test node may also contain driver circuits for transfer of rapid data to a memory of the test computer for subsequent processing at a lower speed and may also contain equipment to assist in the use of a so-called signature analysis system.