Pager receiver having a common timer circuit for both sequential lock-out and out-of-range
US4928086A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 1989 |
| Grant date | May 22, 1990 |
| Priority date | — |
| Expiry date | Jan 30, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG08B3/1066
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A pager receiver includes at least one lock-out circuit, an out-of range circuit, and a single timer coupled to the lock-out and out-of range circuits and responsive to timing signals generated by the pager for generating an initiated one of either the lock-out timer interval or out-of range time interval. Each lock-out circuit of the pager receiver corresponds to an address function programmed therein and is activated by the function detect signal generated in response to the initial decoding of the corresponding address function to initiate the generation of the lock-out time interval by the single timer and to inhibit the corresponding alert annunciation from responding to subsequently generated function detect signals corresponding thereto for the duration of the lock-out time interval. The single timer is also initiated to generate the out-of-range time interval at the generation of each sync pulse timing signal by the pager receiver, but only in the absence of an activated lock-out circuit. Accordingly, the single timer is disabled from initiating the generation of the out-of-range time interval for the duration of an initiated lock-out time interval. Still further, the singl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.