Die corner design having topological configurations
US4928162A · kind A · utility
19Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1988 |
| Grant date | May 22, 1990 |
| Priority date | — |
| Expiry date | Feb 22, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved semiconductor die for plastic encapsulated semiconductor devices which impedes the inherent delamination caused by the differing expansion coefficients of the semiconductor die and plastic encapsulation. Topological configurations are processed in the die corners of the semiconductor die which are void of circuitry. The topological configurations act as barriers and slow the delamination progression. This leaves the operational circuitry unaffected for an increased time thereby increasing device lifetime.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.