Floating point microprocessor with directable two level microinstructions
US4928223A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1986 |
| Grant date | May 22, 1990 |
| Priority date | — |
| Expiry date | Aug 28, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3889
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor integrator circuit includes split nanocode memories which enables simultaneous execution of an arithmetic operation and an operand fetch for maximizing through-put. The circuit also includes a shared sequencing arithmetic logic unit which handles all microcode sequencing plus memory address sequencing. The circuit also provides nanocode sequencing which enables storage of constants and data in a microcode space which can include an off-chip writable control store. In addition, two level microcode is utilized to enable long routines to be vertically encoded without the overhead of a large number of read only memory outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.