Static ram with high speed, low power reset
US4928266A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1988 |
| Grant date | May 22, 1990 |
| Priority date | — |
| Expiry date | May 26, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static memory device is disclosed having an array of static memory cells, each memory cell having first and second cross-coupled inverters. All of the memory cells have distinct power voltage connections to the first and second inverters of each memory cell. When a reset signal occurs, the device's reset apparatus generates a voltage imbalance on the power voltage connections so that distinct voltage levels are applied to the first and second cross-coupled inverters of each memory cell. The voltage imbalance causes all of the memory cells in the array to be set into a predetermined state. In a preferred embodiment, the power voltage connections include a common high voltage power connection to all of the memory cells and distinct low voltage power connections to the first and second inverters of each memory cell. The reset apparatus applies a higher voltage potential on the low voltage power connection to the first inverters than the voltage potential applied on the low voltage power connection to the second inverters of each memory cell. As a result all memory cells are set into a state in which the internal storage nodes of the first inverters retain a higher voltage than the i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.