Clock circuit having a clocked output buffer
US4929854A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Apr 10, 1989 |
| Grant date | May 29, 1990 |
| Priority date | — |
| Expiry date | Apr 10, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device includes an internal logic circuit for carrying out a logic operation and generating an output signal based on the logic operation, and an output buffer circuit connected to the internal logic circuit, for outputting the output signal through an output terminal in synchronism with a clock signal. The semiconductor integrated circuit also includes a non-overlap clock generator, and a third-clock generator. The non-overlap clock generator generates a first internal clock signal which falls in synchronism with a falling edge of an external clock signal, and generates a second internal clock signal which falls in synchronism with a rising edge of the external clock signal, the internal logic circuit carrying out the logic operation in synchronism with the first and second internal clock signals. The third-clock generator generates a third internal clock which rises in synchronism with the falling edge of the second internal clock signal and which falls in synchronism with the falling edge of the first internal clock signal, the third internal clock being supplied, as the clock signal, to the output buffer circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.