Data path chip test architecture
US4929889A · kind A · utility
50Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1988 |
| Grant date | May 29, 1990 |
| Priority date | — |
| Expiry date | Jun 13, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for testing nodes, or test points, of an integrated circuit are presented. The invention includes a test/load bus which is used to sequentially load test data and other data onto the integrated circuit chip, to sample test points and to read data previously loaded onto the chip. The test/load bus and its control logic are used for both testing the chip and for loading and dumping data from the chip so that the test capability adds little to the area of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.