Phase-locked loop circuit
US4929917A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1988 |
| Grant date | May 29, 1990 |
| Priority date | — |
| Expiry date | Dec 22, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B7/005
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop circuit (PLL) to which a phase-synchronization signal is intermittently supplied, both of the natural angular frequency of the PLL and the damping factor of the same are so determined as to prevent a phase difference produced at the next sampling point from exceeding the linear property range of a phase comparator even when the extraneous electrical disturbance enters the PLL. In addition, when the level of a clock control signal supplied to a variable frequency oscillator which varies the clock signal of the PLL in phase and frequency exceeds a predetermined value, the level of the clock control signal is limited to the predetermined value. As a result, it is possible to prevent the output signal of the phase difference from having any discontinuity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.