Setting and dynamically adjusting VCO free-running frequency at system level
US4929918A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1989 |
| Grant date | May 29, 1990 |
| Priority date | — |
| Expiry date | Jun 7, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1258
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and means for setting the free-running frequency of a voltage controlled oscillator (VCO) without requiring laser trimming or the like is described. The VCO forms part of an interconnected phase-locked loop (PLL) and frequency-locked loop (FLL). At system power on, the PLL is automatically disabled and a digital-to-analog (DAC) in the PLL is set to a value corresponding substantially to the center of a preselected lock range. The FLL, which includes a second DAC, then operates to generate a bias voltage for incrementing or decrementing the VCO output frequency until the VCO pulse count stored in a register equals an expected count; whereupon the VCO will be set at its free-running frequency. When the PLL is enabled, a phase error generator generates a digital phase error signal from the input data. A digital integrator converts the phase error signal to a digital frequency error signal. These error signals are added and the result is supplied to the DAC in the PLL for providing an analog output indicative of PLL frequency error. The outputs from both DACs are summed and the resultant current is converted to a bias voltage to adjust the VCO frequency as necessary for normal…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.