Electrostatic discharge protection circuit for an integrated circuit
US4930036A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 13, 1989 |
| Grant date | May 29, 1990 |
| Priority date | — |
| Expiry date | Jul 13, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A terminal of an integrated circuit is protected from electrostatic discharge voltages at the terminal by a protection circuit which includes a bidirectionally conductive transistor as a discharge current shunting device. A bidirectionally conductive controlled path is provided between the terminal and one of two voltage supply terminals. The transistor has a biassing resistor connected between the terminal and its control electrode. A normally reverse biassed diode is connected between the control electrode on another of the voltage supply terminals. For an n-channel FET or an npn bipolar transistor, when a positive electrostatic discharge is applied to the terminal, a current flowing through the biassing resistor turns on the transistor to provide a discharge path from the terminal to the voltage supply terminal. When a negative electrostatic discharge is applied to the terminal, the diode is forward biassed and a resulting current flow through the biassing resistor turns on the transistor to provide a discharge path from the voltage supply terminal to the terminal. The transistor may be either a symmetrical bipolar transistor or an enhancement mode FET. An embodiment of the circ…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.