Nonvolatile semiconductor memory device with a double gate structure
US4930105A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1988 |
| Grant date | May 29, 1990 |
| Priority date | — |
| Expiry date | Apr 7, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.