Digital phase lock loop
US4930142A · kind A · utility
18Cited by
12References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1988 |
| Grant date | May 29, 1990 |
| Priority date | — |
| Expiry date | Dec 6, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus and/or method for generating a digital clock signal which is frequency and phase referenced to an external digital data signal is disclosed. The external digital data signal is typically subject to variations in data frequency and high frequency jitter unrelated to changes in the data frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.