Method for manufacturing integrated bipolar and MOS transistors
US4931407A · kind A · utility
23Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1988 |
| Grant date | Jun 5, 1990 |
| Priority date | — |
| Expiry date | Jun 24, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0109
Abstract
A method for manufacturing MOS and bipolar transistors is proposed which includes MOS and bipolar transistors. The method comprises implanting impurity ions in a channel formation region with a dummy gate insulating film interposed and, subsequent to forming a gate oxide film on the surface of the resultant structure, impurity ions are implanted into an internal base region of the bipolar transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.