Process for producing semiconductor integrated circuit device having copper interconnections and/or wirings, and device produced
US4931410A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1988 |
| Grant date | Jun 5, 1990 |
| Priority date | — |
| Expiry date | Aug 25, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/95
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a process for forming a patterned copper layer on a substrate, using a patterned photoresist layer for forming the patterned copper layer. Etching mask and anti-oxidizing layers are formed on a copper layer (from which the patterned copper layer is formed) prior to forming the patterned photoresist layer. The uppermost one of the etching mask and anti-oxidizing layers is etched using the patterned photoresist layer as a mask, and then the patterned photoresist layer is removed, by oxygen plasma treatment, with the copper layer covered by the lower one of the etching mask and anti-oxidizing layers. By removing the patterned photoresist layer, by oxygen plasma treatment, while the copper layer is covered, oxidation of the copper layer during the oxygen plasma treatment can be avoided. The patterned copper layer can be an interconnection or wiring of a semiconductor device, formed on a semiconductor substrate having semiconductor elements therein. Also disclosed is the product formed by this method, such product including at least a residue of the etching mask layer in addition to the anti-oxidizing layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.