MIS transistor driven inverter circuit capable of individually controlling rising portion and falling portion of output waveform
US4931668A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 1988 |
| Grant date | Jun 5, 1990 |
| Priority date | — |
| Expiry date | Jan 13, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A resistor is connected to an input portion of a CMOS inverter. An input of the CMOS inverter is affected by a time constant of an RC circuit comprising the resistor and gate stray capacitance of the CMOS inverter. In addition, there is provided an n channel MOS transistor having a drain and a source connected to both ends of the resistor, respectively, and a gate connected to an input signal source. Only in the rising portion of an input signal, the n channel MOS transistor is turned on, so that the resistor is bypassed. Thus, a waveform of output of the CMOS inverter is not delayed at the falling portion. Only at the rising portion, the waveform thereof is delayed due to the time constant of the above described RC circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.