Diagnostic fault test system and circuit
US4932246A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1989 |
| Grant date | Jun 12, 1990 |
| Priority date | — |
| Expiry date | Feb 22, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/72
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Diagnostic fault test system and circuit sequentially tests a plurality of drivers (12) and their associated solenoid loads (13). Control signals (PM, SM) are provided to the drivers by a computer controller (11) to achieve desired solenoid actuation. The controller temporarily alters the control signals such that all of the drivers are forced into an on or off state for a first time period (t.sub.A or t.sub.B). After a delay (t.sub.Don or t.sub.Doff) a signal (V.sub.M) associated with each driver stage is monitored to determine if the driver and its load are operating properly. Then the controller resumes normal control of the drivers. The duration of the forced on/off state is short enough so as not to cause a change in the actuated/nonactuated state of the solenoid loads. Each monitored signal from the driver is sequentially compared to a high and low threshold (50, 51) to indicate either proper operation or the identification of one of two different types of fault which may occur. Drivers are preferably tested in both on and off states for proper operation and identification of a total of four different possible faults. Present system allows rapid testing of all drivers and the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.