Method of making self-aligned tungsten interconnection in an integrated circuit
US4933303A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 1989 |
| Grant date | Jun 12, 1990 |
| Priority date | — |
| Expiry date | Jul 25, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process is disclosed for making a self-aligned metal (preferably tungsten) connection in an integrated circuit. A contact hole formed in a first dielectric layer on a substrate is filled with metal, after which the first dielectric layer and the metal-filled contact hole are covered with a second dielectric layer. A photoresist layer is formed over the second dielectric layer and is patterned. A trench is formed in the exposed second dielectric layer and a thin layer of silicon or a metal such as tungsten is then sputtered or evaporated to form a layer of the silicon or metal on the upper surface of the patterned photoresist and the bottom and side walls of the trench. The patterned photoresist is removed and the trench is filled with metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.