Gate array device having macro cells for forming master and slave cells of master-slave flip-flop circuit
US4933576A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 1989 |
| Grant date | Jun 12, 1990 |
| Priority date | — |
| Expiry date | May 9, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/923
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate array device forms an arbitray logic circuit depending on interconnections formed thereon, and comprises a semiconductor chip having an approximate rectangular shape, an input terminal region including a plurality of input terminals formed at a peripheral portion of the semiconductor chip, an output terminal region including a plurality of output terminals formed at a peripheral portion of the semiconductor chip, and a macro cell region including a plurality of macro cells formed at a central portion of the semiconductor chip. The macro cells include first macro cells and second macro cells, where each of the first macro cells include a minimum number of elements for forming a master part of a master-slave flip-flop circuit and each of the second macro cells include at least a minimum number of elements for forming a slave part of the master-slave flip-flop circuit. The first macro cells and the second macro cells make macro cell pairs and are regularly arranged within the macro cell region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.