n-Dimensional modular multiprocessor lattice architecture
US4933836A · kind A · utility
35Cited by
7References
3Claims
0Family size
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Key dates
| Filing date | May 17, 1989 |
| Grant date | Jun 12, 1990 |
| Priority date | — |
| Expiry date | May 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4494
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of n-dimensional modular entities are internally interconnected via as many as n duel port random access memory devices (DPRs), each memory device dedicated solely to the interchange of information between two modular entities in an n-dimensional lattice of modular entities. One or more of the modular entities may itself be a separate multiprocessor architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.